VLSI PROJECT
Design of
Reconfigurable Digital IF Filter With Low Complexity
Abstract:
Due to limited frequency
resources, new services are being applied to the existing frequencies, and
service providers are allocating some of the existing frequencies for newly
enhanced mobile communications. Because of this frequency environment, repeater
and base station systems for mobile communications are becoming more
complicated, and frequency interference caused by multiple bands and services
is getting worse. Therefore, a heterodyne receiver using intermediate frequency
(IF) filters with high selectivity has been used to minimize the interference
between frequencies. However, repeater and base station systems in mobile
communications employing fixed IF filters cannot actively cope with the usage
of multiple frequency bands, the application of various services, and frequency
recycling. Therefore, this brief proposes a reconfigurable digital IF filter
with variable center frequency and bandwidth while achieving high selectivity
as existing IF filters. The center frequency of a filter can vary from 10 MHz
to 62.5 MHz, and the filter bandwidth can be selective to one of 10 MHz, 15
MHz, and 20 MHz. The proposed digital filter also reduces the complexity of
adders and multipliers by 38.81% and 41.57%, respectively, compared to an
existing digital filter by using a filter bank and a multi stage structure.
This digital IF filter is fabricated on a 130-nm CMOS process and occupies 5.90
mm 2 .
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